QEMU adds POWER10 support

"Wait," you say, "POWER10 isn't out yet!" No, it's not; even Axone (variously known as the AIO POWER9 "Advanced I/O" and "POWER9 Prime") is still yet to come out later this year (for that matter, we haven't heard much more about the LaGrange-based Raptor Condor which was announced at the same time). However, there are almost certainly simulations of the forthcoming 7nm POWER10 in IBM's chip labs, and some of that is public in the QEMU sources.

To be sure, what's currently in QEMU is at most rudimentary. The patches that have landed in the new 5.0 release describe the POWER10 as "very similar" to POWER9. The DD1.0 initial stepping (PVR base 0x00800000 as opposed to POWER9 0x004E0000) apparently introduces new ISA 3.10 (POWER9 is 3.0), though the MMU and CPU initialization code for POWER10 right now looks like a copy-pasta from the POWER9 section and doesn't expose any obvious new registers. Similarly, I can't find any IBM documentation on 3.10, so we can presume that's either under wraps or yet to be completed. However, a related commit in Skiboot drops the codename for the POWER10 machine under development: much as the POWER8 prototype was Palmetto and the POWER9 prototype was Witherspoon, POWER10's prototype is named Rainier (presumably for the mountain and not the Simpsons character). Given Axone's release expected later in 2020, the first POWER10 system descended from Rainier (like the AC922 was descended from Witherspoon) will likely not appear until 2021.


  1. If there is a "Sforza" CPU then the "Rainier" might be realate to https://en.wikipedia.org/wiki/Archduke_Rainer_Ferdinand_of_Austria ;-)


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